(1) Field of the Invention
This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to an improved process for forming stacked polysilicon contacts.
(2) Description of Related Art
The complexity of present-day integrated circuits requires multiple layers of interconnection conductive patterns in order to connect the discrete semiconductor devices into integrated circuits. In order to minimize use of lateral area over the semiconductor chip surface it is desirable to stack connecting vias directly over one another when connections are made between multiple layers of interconnection conductive patterns. However, in conventional via processing allocation must be made for possible mask misalignment between the conductive interconnection patterns of successive interconnection layers and the etched through hole patterns of successive insulating layers. As a result design rules require that interconnect vias have larger than necessary diameters to assure that they will overlap with conductive lines above and below them with sufficient area to meet designed current carrying requirements. Also, spacings between laterally adjacent interconnection lines have to be enlarged in the region of the interconnect vias in order to avoid undesired shorts.
In conventional processes for formation of the multilevel interconnection structure each via between successive interconnection layers is formed by separate lithographic and etching steps. Each additional lithographic step and each via etch step are costly and add to the complexity of the manufacturing process.
Numerous improvements to methods of forming stacked vias have been invented. For example, U.S. Pat. No. 5,155,056 entitled "Process for Formation of Cells Having Self-Aligned Capacitor Contacts, and Structure Thereof" granted Oct. 13, 1992 to Kim Jeong-Gyoo describes a method of forming self-aligned capacitor contacts, wherein polysilicon layers of differing conductivity types are used.
Also, U.S. Pat. No. 5,432,129 entitled "Method of Forming Low Resistance Contacts At the Junction Between Regions Having Different Conductivity Types" granted Jul. 11, 1995 to Robert L. Hodges describes a method for forming low resistance contacts between polysilicon layers of different conductivity types. The contact resistance is reduced by forming titanium disilicide or other refractory metal suicides at the contact region.
And, U.S. Pat. No. 5,439,848 entitled "Method for Fabricating a Self-Aligned Multi-Level Interconnect" granted Aug. 8, 1995 to Sheng T. Hsu et al describes a method of forming self-aligned multilevel interconnects in which a hole in the top insulator layer defines a succession of self-aligned subsequent holes through underlying conductors and insulating layers.